The present invention relates to image sensor cell array architecture generally and, in particular, to a multi-photodetector unit cell and control thereof.
Image sensors have traditionally used either photodiodes, either alone or in combination with active transistor element, or charge couple device (CCD) technology. For the last thirty years CCD has been the dominant image sensor technology.
The CCDs have many advantages, such as small pixel size, high sensitivity, and the ability to generate high-fidelity images. They also have many disadvantages, such as special manufacturing process requirements, high power dissipation, inability to integrate on the same chip additional functionality such as driving the processing, and complicated control circuitry. Furthermore, CCDs are manufactured by just a few manufacturers, and are not broadly accessible by independent design houses.
One of the emerging competing technologies, Complementary Metal Oxide Semiconductor (CMOS)-process-based active pixel sensor (APS) technology, promises low power, ability to integrate on the same chip the sensor and control circuitry, ability to form huge sensor arrays etc. One of the main goals to be accomplished in the APS design is a small pixel, comparable in size to the one accomplished with CCDs, with a high signal to noise ratio. This is difficult since the APS unit cell incorporates several active transistors. The signal-to-noise ratio requirement dictates the collection of as many photon-generated electrons as possible over the integration capacitor. This requires long integration time for weak photocurrents, and sizable capacity pixel-space-consuming capacitors.
Considerable research efforts have been directed towards reduction of the APS pixel size, and improvements in fill factor and quantum efficiency. Example of such are described in D. Scheffer et al., xe2x80x9cRandom addressable 2048xc3x972048 active pixel image sensor,xe2x80x9d IEEE Trans. Elec. Dev. Vol. 44, no. 10, October 1997, pp. 1716-1720, and in Y. lida et al., xe2x80x9cA xc2xc-inch 330k square pixel progressive scan CMOS active pixel image sensor,xe2x80x9d IEEE JSSC, Vol. 32, no. 11, November 1997, pp. 2042-2047.
The following is a partial listing of non-standard and standard technology alternatives used to achieve the above mentioned improvements.
Because standard technology fails to support special new applications, ample of research effort has been put in to the development of non-standard technology.
Amorphous silicon photoconductor, photodiode, or phototransistor: This endeavor produces a reduced unit cell size and improved fill factor through photodetector vertical integration on top of the active readout circuit. The quantum efficiency is close to 100%, and the dark current is lower in comparison to the dark current accomplished with the single-crystal material. However, due to material charge trapping and structure irregularities, the amorphous silicon based photodetectors suffer from high fixed pattern noise (FPN). Backside-illuminated photodetectors: In this technology, whether CCDs or APS-based, the sampling and readout is located on the front side, and the photodetector occupies the backside of the image sensor. The image sensor is illuminated from its backside. Therefore, the fill factor, and quantum efficiency of nearly 100%, can be accomplished.
However, in order to produce the backside-illuminated photodetector, a process known as wafer thinning is required, which is a complex, expensive process. Therefore, backside-illuminated image sensors are employed for very specialized scientific and aerospace cost-insensitive applications. Furthermore, wafer thinning results in substantial crystalline irregularities nearby the wafer""s surface and in a substantial excess noise due to surface recombination. Charge modulation devices (CMD): The CMD is distinguished by its simple structure. Due to its simple structure (a single transistor) very small pixels are achievable. This facilitates the implementation of huge-format arrays. However, the CMD image sensors are less sensitive to shorter wavelengths of light and require a specialized fabrication process.
A lot of effort goes into research directed at the implementation of high-performance image sensors using a standard CMOS process for fabrication. This direction is of primary importance, since it promises low fabrication costs for on-chip cameras with readily available technology. Constructing high-quality APS image sensors takes the following directions:
Passive photodiode-detector image sensors: These image sensors use photodiodes as the sensing elements. Passive photodiode-based pixel elements were investigated in the 1960s. These pixels are very simple; they incorporate a single diode and a single transistor. The passive pixel design allows the highest fill factor for a given pixel size, or the smallest pixel size for a given fill factor.
However, this approach is limited by the relatively high readout noise. Also, the passive unit cell directly drives a full column-capacitance in the image sensor array. Since this capacitance Is directly proportional to the number of column pixels, this limits the readout speed and results in significant readout noise. Therefore, the passive pixel approach is not well suited to the design of large-format image sensors.
Active-pixel photodiode-based image sensors: Photodiode-based APS image sensors feature a high quantum efficiency for the red, the green and even for the blue-wavelength photons. The name xe2x80x9cactive pixel sensorxe2x80x9d originates from its having at least one active transistor incorporated in every unit cell. The transistor performs an amplification or buffering function.
There are many types of active circuits. The simple ones incorporate up to three transistors in the unit cell. The APS photodetectors are limited in their fill factor per fixed unit cell size, or are limited in the minimum cell size per fixed fill factor. It is a major objective to reduce the overall unit cell complexity, to accomplish high-resolution, a high fill factor and a high quantum efficiency.
Interestingly enough, small pixels result in a reduced readout noise and speed improvement, due to a reduced column capacitance. Although designs with a minimal number of transistors and very small pixels have been reported (5.6xc3x975.6 xcexcm), these designs also feature a very small fill factor (15.8%).
Active-pixel photogate-type image sensors: The basic concept behind this circuit is to combine the sensing and charge storage functions. The front-side light-illuminated transistor collects charge proportional to light-intensity below the gate. At the readout time, the charge collected and stored below the photogate is transferred to the floating diffusion node The floating diffusion is tied to the source follower circuit input. The source follower buffers the floating diffusion from the high capacitance array column.
Overall, the photogate pixel design incorporates five transistors including the photogate sensing/charge-storage device. The low readout noise and lack of image lag demonstrated by the photogate structure have stirred a lot of interest and have resulted in significant research effort directed at. the improvement of the photogate-based design. Relatively small pixels have been developed (10xc3x9710 xcexcm using the 0.5 xcexcm CMOS process technology). However, this approach demonstrates however low quantum efficiency for the blue light wavelength photons, which are absorbed by the polysilicon-plated photogate.
In order to overcome this problem, some engineering compromises are made and APS-based sensors that combine the photogate and the photodiode design have been invented. This design uses photogate sites to collect the red and the green wavelength photons and photodiode sites to collect the blue wavelength photons.
The ability to modify the image sensor""s resolution is defined as multi-resolution. The application of multi-resolution has been justified by the ability to trade high resolution for the increase of the video frame rate and the image processing. Far more important, the multi-resolution approach makes it possible to trade the resolution for signal-to-noise ratio. This is especially crucial in low light conditions, when the electrical signal proportional to the light intensity may be quite weak This results in a noisy, low-quality image. Sometimes it is preferable to get a lower resolution but less-noisy image.
One of the methods used, as described by S. Kemeny et al: xe2x80x9cCMOS Active Pixel Sensor Array with Programmable Multiresolution Readoutxe2x80x9d, JPL, California Institute of Technology, Pasadena Calif. 91109 USA, 1994, and by R. Paniacci et al: xe2x80x9cProgrammable multiresolution CMOS active-pixel sensorxe2x80x9d, SPIE Vol. 2654, trades resolution for speed. The method is based upon pixel signal block averaging. The described method is complicated, and does not yield a better signal-to-noise ratio
The second method, as described by Zhimin Zhou et al: xe2x80x9cFrame-Transfer CMOS Active Pixel Sensor with Pixel Binningxe2x80x9d, IEEE Trans. Elec. Dev., Vol. 44, No. 16, October 1997, pp. 1764-1768, enables the summation of the accumulated charge in several pixels. The accumulated charge summation is performed first by sampling the charge accumulated during charge integration into a memory cell, and second, by summing up the transferred charge on vertical and horizontal charge integration amplifiers (CIAs).
Since, the charge summation is linear, while the noise sums up as a square root of the noise energies, the pixel charge summation yields an improvement in the signal-to-noise ratio.
It is an objective of the present invention to provide a CMOS image sensor architecture that produces a substantially optimal combination of sensitivity and signal-to-noise ratio, along with relatively high fill factor. There is therefore provided, in accordance with an embodiment of the present invention, a multi-cell cluster that may include a plurality of light-etecting unit cells and a circuit. Typically, each of the cells produces charge representative of the detected light. The circuit may be shared by the plurality of unit cells, and used to read-out the charge in real-time. The cluster may also include a switch associated with each unit cell, such that each switch connects its associated unit cell to the circuit. The switch may also be controlled in a time-multiplexing manner. Each unit cell may include either a photodetector, a photodiode, or a photogate. The circuit may include a shared storage device, a shared reset circuit, or a readout circuit. Typically, the shared storage device may be for accumulating the charge in the focal plane.
There is further provided, in accordance with an embodiment of the present invention, a sensing array including a multiplicity of clusters, sampling lines and sensing lines. The clusters may include a plurality of unit cells and a circuit. The unit cells may detect light, and produce charge representative of that light. The circuit may be shared by the unit cells and may control the operation of the unit cells. The circuit may also accumulate the charge. Each sampling line may be connected to a row of clusters for sampling the accumulated charge in the row. Each sensing line may be connected to a column of clusters for sensing the sampled charge present in the columns. The sampling and the sensing lines may also carry programming signals for controlling the plurality of unit cells.
There is also provided, in accordance with an embodiment of the present invention, a method for operating an image sensor. The method includes the steps of integrating charge from one or more unit cells of a cluster and, during the step of integrating, summing charge from at least one of the unit cells in the focal plane. The method may also include reading out the summed charge. One or more of the unit cells may be preprogrammed unit cells, and the step of reading out may include reading out the summed charge in real time.
The step of integrating may include the step of integrating in a time-multiplexing manner, or may include the step of integrating charge from each unit cell separately. Alternatively, the step of integrating may include the step of simultaneously integrating charge from two or more of the unit cells, or may include the step of simultaneously integrating charge from all of the unit cells in the cluster. The method may include the step of combining the readout into a single image.
The method may further include the step of dynamically controlling selection of the number of unit cells for the step of charge integrating, and this step of dynamically controlling may include the step of selecting the number of unit cells depending on the light conditions. All of the steps may be performed in real-time.
Also included in the method may be the step of improving the signal-to-noise ratio of the image sensor by increasing the number of cells in the step of charge integrating. This is done in order to linearly increase the amount of summed charge while the noise increases moderately as a square root function. The method may further include a step of improving the resolution of the image sensor by reading-out each cell separately, in a time-multiplexing manner.